There has been conventionally widely used, as a power-on reset circuit, a type of the power-on reset circuit for applying a power supply voltage to a capacitor via a resistor, thereby generating a reset signal utilizing a charging time of the capacitor. However, there arises an inconvenience in such a power-on reset circuit that if the rising speed of the power supply voltage, when the power is applied thereto, is slower than the charging time of the capacitor, the output of the reset signal is stopped even when the power supply voltage is, e.g. less than 1V, so that an efficient rest signal can not be outputted. To avoid such an inconvenience, there is proposed, a power-on reset circuit, e.g. as disclosed in JP-A H11-68539. FIG. 1 shows a circuit diagram of a conventional power-on reset circuit as disclosed in this publication.
This power-on reset circuit comprises a power supply voltage detection circuit 60, a capacitor charging time constant circuit 70 and an inverter 75 serving as an output circuit. The power supply voltage detection circuit 60 comprises a PMOS 61 a source of which is connected to a power supply potential VCC, and a PMOSs 62 and 63 forming rectifying devices which are serially connected between a drain of the PMOS 61 and a ground potential GND. The drain of the PMOS 61 is connected to a node N60 to which a source of the PMOS 62 is connected. A gate and a drain of the PMOS 62 are connected to a source of the PMOS 63, and a gate and a drain of the PMOS 63 are connected to the ground potential GND.
The capacitor charging time constant circuit 70 comprises a PMOS 71 a gate of which is connected to the node N60, and a PMOS 72 a gate of which is connected to the power supply potential VCC. A source of the 71 is connected to the power supply potential VCC and a drain of the PMOS 72 is connected to the ground potential GND. A drain of the 71 and a source of the PMOS 72 are connected to a node N70 to which the gate of the PMOS 61 is connected. Further, a capacitor 73 is connected between the node N70 and the ground potential GND. A potential of the node N70 is converted into a detail signal of “H” and “L” by the inverter 75, and outputted as a reset signal.
An operation of the power-on reset circuit is described next.
When the power supply potential VCC is 0V which is the same as the ground potential GND, the PMOS 72 is in a diode connection state whereby an electric charge charged in the capacitor 73 is discharged through the PMOS 72. Consequently, the potential of the node N70 becomes less than a threshold voltage of the PMOS 72 which is applied to the gate of the PMOS 61 as a feedback voltage.
If the power supply potential VCC rises from this state, the inverter 75 outputs “H” but the potential thereof rises together with the power supply potential VCC. When the power supply potential VCC is greater than a sum of the threshold voltage of the PMOS 72 and that of the PMOS 61, the PMOS 72 is in an OFF state and the PMOS 61 is in an ON possible state.
Supposing that the sum of the threshold voltages PMOSs 62 and 63 is set to be greater than the sum of the threshold voltages of the PMOSs 61 and 72, the potential of the node N60 remains in a state where it is clamped by the diode voltages of two PMOSs 62 and 63 connected to the node N60. That is, each of the PMOSs 62 and 63 is not turned on while the potential of node N60 becomes a potential which is substantially proportional to the rise of the power supply potential VCC. This state continues during a period starting from the time when the power supply potential VCC reaches the sum of the threshold voltages of the PMOSs 61 and 72 and ending at the time when exceeds the sum of the threshold voltages of the PMOSs 62 and 63. As a result, the potential of the gate of the PMOS 71 is substantially the same as the power supply potential VCC, and is maintained in an OFF state.
When the power supply potential VCC further rises and exceeds the sum of the threshold voltages of the PMOSs 62 and 63, these PMOSs 62 and 63 are turned on so that a current flows to the PMOS 61. As a result, a voltage applied between the source and the gate of the PMOS 71. Still further, when the power supply potential VCC rises to exceed the sum of the threshold voltages of the PMOSs 62, 63 and 71, the PMOS 71 is completely turned on.
When the PMOS 71 is turned on, the charging of the capacitor 73 starts whereby the potential of node N70 rises by the time constant which is determined by an on resistance of the PMOS 71 and a capacitance of the capacitor 73. When the potential of the node N70 reaches the threshold voltage of the inverter 75, a reset signal outputted from the inverter 75 is changed from “H” to “L”. As a result, the one shot reset signal outputted from the inverter 75 is cancelled.
When the potential of the node N70 further rises as the charging of the capacitor 73 advances, the potential of the gate of the PMOS 61 rises so that a voltage between the gate and source of the PMOS 61 becomes small and the PMOS 61 is turned off ultimately. When the PMOS 61 turned off, the potential of node N60 also lowers so that the PMOS 71 is also turned off to keep the level of the node N70 at “H”.
Inasmuch as the power-on reset circuit is configured such that the charging of the capacitor 73 inside the capacitor charging time constant circuit 70 is started when the power supply potential VCC exceeds the sum of the threshold voltages of the PMOSs 62, 63 and 71 which is detected by the power supply voltage detection circuit 60, a reset signal can be surely generated even if the rising of the power supply potential VCC is slow.
However, there are following problems in the conventional power-on reset circuit. That is, if the reset signal is once cancelled when the power supply potential VCC rises, the reset signal is not outputted again unless the power supply potential VCC sufficiently lowers to discharge the electric charge of the capacitor 73 even if the power supply potential VCC lowers thereafter. Accordingly, in a case where the power supply potential VCC does not rise monotonously but rises un-monotonously while rising and lowering, there is a likelihood that an efficient reset signal can not be outputted.
Further, since the timing of the start of the charging of the capacitor 73 is determined by the threshold voltages of the PMOSs 62, 63 and 71, there is a problem that a cancellation voltages of the reset signal undergoes a lot of changes by the variation in a manufacturing process of the power-on reset circuit.